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oki semiconductor fedl9092-01 issue date: nov. 4, 2003 ml9092-01/02/03/04 lcd driver with key scanner and ram 1/66 general description the ml9092-01/02/03/04 are lcd drivers that have internal ram and a key scan function. they are best suited for car audio displays. since 1-bit data of the display data ram corresponds to the light-on or light-off of 1-dot of the lcd panel (a bit map system), a flexible display is possible. a graphic display system of a maximum of 60 10 dots (56 10 dots for ml9092-01, 60 10 dots for ML9092-02/03/04). can be implemented. the ml9092-01/02 do not require any power supply circuit to drive the lcd, because they have internal voltage doublers. (if a large-sized panel is driven, use the ml 9092-03, to which the lcd driving voltage is supplied externally.) the internal key scan circuit (5 5 key scanning for ml9092-01/04, 6 4 key scanning for ML9092-02/03) has eliminated the needs of key scanning by the cpu, thereby enabling the effici ent use of the cpu ports. features ? logic voltage : 4.5 to 5.5 v ? lcd drive voltage : 4.5 to 16.5 v (positive voltage) ? segment output : 56 outputs for ml9092-01; 60 outputs for ML9092-02/03/04 ? common output : 10 outputs ? built-in bit-mapped ram : 60 10 = 600 bits (for ml9092-01 only: 56 10 = 560 bits for the ram display area) ? 4-pin serial interface with cpu: cs , cp , di/o, kreq ? built-in lcd drive bias resistors ? built-in voltage doubler circuit ? for the ml9092-01/04, the built-in 5 5 key scanner makes it possible to read the status of 25 key switches and 1-channel rotary encoder. in addition, the ml9092-01/ 04 have an 8-bit, 3-channlel pwm circuit built in. for the ML9092-02/03, the built-in 6 4 key scanner makes it possible to read the status of 24 key switches and 1-channel rotary encoder. ? port a output : 1 pin, output current = ?15 ma : can be used for led driving ? port b output : 3 pins, output current = ?2 ma : applies to ml9092-01/04 (capable of pwm output) ? port c output : 5 pin, output current = ?2 ma : applies to ml9092-01 only ? port d output : 5 pins, output current = ?2 ma : applies to ml9092-01 only ? temperature range : ?40 to +85 c ? package: 100-pin plastic tqfp (tqfp100-p-1414-0.50-k) (product name: ml9092-01tb, ML9092-02tb, ml9092-03tb, ml9092-04tb)
fedl9092-01 oki semiconductor ml9092-01/02/03/04 comparison between the ml9092-01, ML9092-02, ml9092-03, and ml9092-04 item ml9092-01 ML9092-02 ml9092-03 ml9092-04 number of common outputs 10 ma x. 10 max. 10 max. 10 max. number of dots on the lcd screen (selectable by program) 8 56 9 56 10 56 8 60 9 60 10 60 8 60 9 60 10 60 8 60 9 60 10 60 number of port a outputs 1 1 1 1 number of port b outputs 3 0 0 3 number of port c and d outputs (see note below) 5 each 0 0 0 key scan (see note below) 5 5 key scan 4 6 key scan 4 6 key scan 5 5 key scan rotary encoder 1 channel 1 channel 1 channel 1 channel voltage doubler yes yes no no pwm circuit 8-bit, 3-channel no no 8-bit, 3-channel note: the key scan function and port c/d ca nnot be used concurrently. use either.
fedl9092-01 oki semiconductor ml9092-01/02/03/04 3/66 block diagram ml9092-01 pa0 kreq y address counter y address decoder line address decoder y address register input output interface display line counter display data ram 56 10 bit data latch 56 output segment drivers voltage doubler lcd bias voltage driving circuit x address decoder 3 port drivers 10 output common drivers shift register timing generator x address counter x address register i/o buffer com1 v in v 0 v 2 cs osc1 reset cp osc2 test di/o v dd v ss v s1? v c1+ v out pb0 seg1 com10 pb2 seg56 oscillation circuit 1 port driver 5 5 key scan/10 port drivers and encoder switch interface control register ab kps c0/ d0 c1/ d1 c2/ d2 c3/ d3 c4/ d4 r0/ c0 r1/ c1 r2/ c2 r3/ c3 r4/ c4
fedl9092-01 oki semiconductor ml9092-01/02/03/04 4/66 ML9092-02 y address counter y address decoder line address decoder y address register display data ram 60 10 bit data latch shift register 60 output segment drivers x address decoder 10 output common drivers timing generator x address counter x address register i/o buffer com1 seg1 com10 seg60 pa0 kreq input output interface display line counter voltage doubler lcd bias voltage driving circuit v in v 2 cs osc1 reset cp osc2 test di/o v dd v ss v s1? v c1+ v out oscillation circuit 1 port driver 4 6 key scan and encoder switch interface cont r ol register a b c0 c1 c2 c3 r0 r1 r2 r3 r4 v 0 r5
fedl9092-01 oki semiconductor ml9092-01/02/03/04 5/66 ml9092-03 y address counter y address decoder line address decoder y address register display data ram 60 10 bit data latch shift register 60 output segment drivers x address decoder 10 output common drivers timing generator x address counter x address register i/o buffer com1 seg1 com10 seg60 pa0 kreq input output interface display line counter v 2 cs osc1 reset cp osc2 test di/o v dd v ss v 3 v 1 v hin oscillation circuit 1 port driver 4 6 key scan and encoder switch interface control register a b c0 c1 c2 c3 r0 r1 r2 r3 r4 v 0 r5 lcd bias voltage driving circuit
fedl9092-01 oki semiconductor ml9092-01/02/03/04 6/66 ml9092-04 pa0 kreq y address counter y address decoder line address decoder y address register input output interface display line counter display data ram 60 10 bit data latch 60 output segment drivers lcd bias voltage driving circuit x address decoder 3 port drivers 10 output common drivers shift register timing generator x address counter x address register i/o buffer com1 v 0 v 2 cs osc1 reset cp osc2 test di/o v dd v ss v hin pb0 seg1 com10 pb2 seg60 oscillation circuit 1 port driver 5 5 key scan and encoder switch interface control register ab c0 c1 c2 c3 c4 r0 r1 r2 r3 r4
fedl9092-01 oki semiconductor ml9092-01/02/03/04 7/66 pin configuration (top view) ml9092-01 100-pin plastic tqfp seg17 seg16 seg15 seg14 osc1 v dd seg1 seg2 77 76 pa0 kps test osc2 pb0 pb1 pb2 com10 com6 com7 com8 com9 com2 com3 com4 com5 seg54 seg55 seg56 com1 seg3 seg4 seg25 seg24 seg23 seg22 seg21 seg20 seg19 seg18 seg8 seg7 seg6 seg5 seg9 seg12 seg11 seg10 seg13 50 46 47 48 49 42 43 44 45 38 39 40 41 34 35 36 37 30 31 32 33 26 27 28 29 seg26 25 51 b seg27 24 52 a seg28 23 53 r4/c4 seg29 22 54 r3/c3 seg30 21 55 r2/c2 seg31 20 56 r1/c1 seg32 19 57 r0/c0 seg33 18 58 c4/d4 seg34 17 59 c3/d3 seg35 16 60 c2/d2 seg36 15 61 c1/d1 seg37 14 62 c0/d0 seg38 13 63 cs seg39 12 64 cp seg40 11 65 di/o seg41 10 66 kreq seg42 9 67 reset seg43 8 68 v ss seg44 7 69 v 2 seg45 6 70 nc seg46 5 71 v o seg47 4 72 v out seg48 3 73 v s1- 75 v in seg49 2 74 v c1+ seg50 1 81 80 79 78 83 82 89 88 87 86 85 84 93 92 91 90 97 96 95 94 100 99 98 seg51 seg52 seg53 ml9092-01
fedl9092-01 oki semiconductor ml9092-01/02/03/04 8/66 ML9092-02 100-pin plastic tqfp seg51 seg52 seg53 seg54 seg55 seg56 seg57 seg58 seg59 seg60 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 pa0 test osc2 osc1 v dd 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 seg5 0 1 75 v in seg4 9 2 74 v c1+ seg4 8 3 73 v s1- seg4 7 4 72 v out seg4 6 5 71 v o seg4 5 6 70 nc seg4 4 7 69 v 2 seg4 3 8 68 v ss seg4 2 9 67 reset seg41 10 66 kreq seg4 0 11 65 di/o seg3 9 12 64 cp seg3 8 13 63 cs seg3 7 14 62 c0 seg3 6 15 61 c1 seg3 5 16 60 c2 seg3 4 17 59 c3 seg3 3 18 58 r0 seg3 2 19 57 r1 seg31 20 56 r2 seg3 0 21 55 r3 seg2 9 22 54 r4 seg2 8 23 53 r5 seg2 7 24 52 a seg2 6 25 51 b 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 seg2 5 seg2 4 seg2 3 seg2 2 seg21 seg2 0 seg1 9 seg1 8 seg1 7 seg1 6 seg1 5 seg1 4 seg1 3 seg1 2 seg11 seg1 0 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 ML9092-02
fedl9092-01 oki semiconductor ml9092-01/02/03/04 9/66 ml9092-03 100-pin plastic tqfp seg4 seg3 seg2 seg1 seg8 seg7 seg6 seg5 seg12 seg11 seg10 seg9 seg16 seg15 seg14 seg13 50 seg25 seg24 seg23 seg22 seg21 seg20 seg19 seg18 seg17 46 47 48 49 42 43 44 45 38 39 40 41 34 35 36 37 30 31 32 33 26 27 28 29 seg26 25 51 b seg27 24 52 a seg28 23 53 r5 seg29 22 54 r4 seg30 21 55 r3 seg31 20 56 r2 seg32 19 57 r1 seg33 18 58 r0 seg34 17 59 c3 seg35 16 60 c2 seg36 15 61 c1 seg37 14 62 c0 seg38 13 63 cs seg39 12 64 cp seg40 11 65 di/o seg41 10 66 kreq seg42 9 67 rese t seg43 8 68 v ss seg44 7 69 v 3 seg45 6 70 v 2 seg46 5 71 nc seg47 4 72 v 1 seg48 3 73 v 0 seg49 2 74 v hin seg50 1 75 nc 79 78 77 76 83 82 81 80 87 86 85 84 91 90 89 88 v dd 100 99 98 97 96 95 94 93 92 pa0 test osc2 osc1 com7 com8 com9 com10 com3 com4 com5 com6 seg59 seg60 com1 com2 seg55 seg56 seg57 seg58 seg51 seg52 seg53 seg54 ml9092-03
fedl9092-01 oki semiconductor ml9092-01/02/03/04 10/66 ml9092-04 100-pin plastic tqfp seg51 seg52 seg53 seg54 seg55 seg56 seg57 seg58 seg59 seg60 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 pb0 pb1 pb2 pa0 test 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 seg50 1 75 osc2 seg49 2 74 osc1 seg48 3 73 v dd seg47 4 72 v hin seg46 5 71 vo seg45 6 70 nc seg44 7 69 v 2 seg43 8 68 v ss seg42 9 67 rese t seg41 10 66 kreq seg40 11 65 di/o seg39 12 64 cp seg38 13 63 cs seg37 14 62 c0 seg36 15 61 c1 seg35 16 60 c2 seg34 17 59 c3 seg33 18 58 c4 seg32 19 57 r0 seg31 20 56 r1 seg30 21 55 r2 seg29 22 54 r3 seg28 23 53 r4 seg27 24 52 a seg26 25 51 b 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 seg25 seg24 seg23 seg22 seg21 seg20 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 ml9092-04
fedl9092-01 oki semiconductor ml9092-01/02/03/04 11/66 functional descriptions pin functional descriptions ml9092-01 function pin symbol type description 63 cs i chip select signal input pin 64 cp i shift clock signal input pin. this pin is connected to the schmitt circuit internally. 65 di/o i/o serial data signal i/o pin. this pin is connected to the schmitt circuit internally. cpu interface 66 kreq o key scan read and rotary encoder read ready signal output pin. 77 osc1 i oscillation 78 osc2 o connect external resistors with this pin. this pin is connected to the schmitt circuit internally. if using an external clock, input it from the osc1 pin and leave the osc2 pin open. 67 reset i reset input. initial settings can be established by applying a ?l? level to this pin. this pin is connected to the schmitt circuit internally. 80 kps i input pin for switching between key scanning and ports c and d control signal 79 test i test input pin. this pin is connected to the v ss pin. 62?58 c0/d0?c4/d4 i/o input pins that detect status of key switches/port d output pins. when used as input pins, these pins are connected to the schmitt circuit internally. 57?53 r0/c0?r4/c4 o key switch scan signal output pins/port c output pins switch signal 51, 52 a, b i rotary encoder signal input pins. these pins are connected to the schmitt circuit internally. 81 pa0 o port a output pin port output 84?82 pb0?pb2 o port b output pins 50?1 100?95 seg1?seg56 o lcd segment driver output pins lcd driver output 94?85 com1?com10 o lcd comm on driver output pins 76 v dd ? logic power supply pin 68 v ss ? gnd pin 75 v in ? voltage doubler reference voltage input pin 74, 73 v c1 +, v s1 ? ? pins to connect a capacitor for voltage doubler 72 v out ? voltage doubler output pin 71, 69 v 0 , v 2 ? lcd bias pins power supply 70 nc ? should be left open.
fedl9092-01 oki semiconductor ml9092-01/02/03/04 12/66 ML9092-02 function pin symbol type description 63 cs i chip select signal input pin 64 cp i shift clock signal input pin. this pin is connected to the schmitt circuit internally. 65 di/o i/o serial data signal i/o pin. this pin is connected to the schmitt circuit internally. cpu interface 66 kreq o key scan read and rotary encoder read ready signal output pin. 77 osc1 i oscillation 78 osc2 o connect external resistors with this pin. this pin is connected to the schmitt circuit internally. if using an external clock, input it from the osc1 pin and leave the osc2 pin open. 67 reset i reset input. initial settings can be established by applying a ?l? level to this pin. this pin is connected to the schmitt circuit internally. control signal 79 test i test input pin. this pin is connected to the v ss pin. 62?59 c0?c3 i input pins that detect status of key switches. these pins are connected to the schmitt circuit internally. 58?53 r0?r5 o key switch scan signal output pins switch signal 51, 52 a, b i rotary encoder signal input pins. these pins are connected to the schmitt circuit internally. port output 80 pa0 o port a output pin 50?1 100?91 seg1?seg60 o lcd segment driver output pins lcd driver output 90?81 com1?com10 o lcd comm on driver output pins 76 v dd ? logic power supply pin 68 v ss ? gnd pin 75 v in ? voltage doubler reference voltage input pin 74, 73 v c1 +, v s1 ? ? pins to connect a capacitor for voltage doubler 72 v out ? voltage doubler output pin 71, 69 v 0 , v 2 ? lcd bias pins power supply 70 nc ? should be left open.
fedl9092-01 oki semiconductor ml9092-01/02/03/04 13/66 ml9092-03 function pin symbol type description 63 cs i chip select signal input pin 64 cp i shift clock signal input pin. this pin is connected to the schmitt circuit internally. 65 di/o i/o serial data signal i/o pin. this pin is connected to the schmitt circuit internally. cpu interface 66 kreq o key scan read and rotary encoder read ready signal output pin. 77 osc1 i oscillation 78 osc2 o connect external resistors with this pin. this pin is connected to the schmitt circuit internally. if using an external clock, input it from the osc1 pin and leave the osc2 pin open. 67 reset i reset input. initial settings can be established by applying a ?l? level to this pin. this pin is connected to the schmitt circuit internally. control signal 79 test i test input pin. this pin is connected to the v ss pin. 62?59 c0?c3 i input pins that detect status of key switches. these pins are connected to the schmitt circuit internally. 58?53 r0?r5 o key switch scan signal output pins switch signal 51, 52 a, b i rotary encoder signal input pins. these pins are connected to the schmitt circuit internally. port output 80 pa0 o port a output pin 50?1, 100?91 seg1?seg60 o lcd segment driver output pins lcd driver output 90?81 com1?com10 o lcd comm on driver output pins 76 v dd ? logic power supply pin 68 v ss ? gnd pin 74 v hin ? high-voltage power supply pin 73, 72, 70, 69 v 0 , v 1 , v 2 , v 3 ? lcd bias pins power supply 75, 71 nc ? should be left open.
fedl9092-01 oki semiconductor ml9092-01/02/03/04 14/66 ml9092-04 function pin symbol type description 63 cs i chip select signal input pin 64 cp i shift clock signal input pin. this pin is connected to the schmitt circuit internally. 65 di/o i/o serial data signal i/o pin. this pin is connected to the schmitt circuit internally. cpu interface 66 kreq o key scan read and rotary encoder read ready signal output pin. 74 osc1 i oscillation 75 osc2 o connect external resistors with this pin. this pin is connected to the schmitt circuit internally. if using an external clock, input it from the osc1 pin and leave the osc2 pin open. 67 reset i reset input. initial settings can be established by applying a ?l? level to this pin. this pin is connected to the schmitt circuit internally. control signal 76 test i test input pin. this pin is connected to the v ss pin. 62?58 c0?c4 i input pins that detect status of key switches. these pins are connected to the schmitt circuit internally. 57?53 r0?r4 o key switch scan signal output pins switch signal 51, 52 a, b i rotary encoder signal input pins. these pins are connected to the schmitt circuit internally. port output 77 80?78 pa0 pb0?pb2 o port a output pin port b output pins 50?1, 100?91 seg1?seg60 o lcd segment driver output pins lcd driver output 90?81 com1?com10 o lcd comm on driver output pins 73 v dd ? logic power supply pin 68 v ss ? gnd pin 72 v hin ? high-voltage power supply pin 71, 69 v 0 , v 2 ? lcd bias pins power supply 70 nc ? should be left open.
fedl9092-01 oki semiconductor ml9092-01/02/03/04 15/66 ? cs chip select input pin. a schmitt circuit is internally connected to this pin. an ?l? level selects the chip, and an ?h? level does not select the chip. during the ?l? level, internal registers can be accessed. ? cp clock input pin for serial interface data i/o. a schmitt circuit is internally connected to this pin. data input to the di/o pin is synchronized to the rising edge of the clock. output from the di/o pin is synchronized to the falling edge of the clock. ? di/o serial interface data i/o pin. a schmitt circuit is internally connected to this pin. this pin is in the output state only during the interval beginning when commands for key scan data read, ram read or rotary encoder are written until the cs signal rises. at all other times this pin is in the input state. (when reset, the input state is set.) the relation between data level of this pin and operation is listed below. data level lcd display key status rotary switch ?h? light on on count value ?l? light off off count value ? kreq key scan read and rotary encode r read ready signal output pin. ? osc1 input pin for rc oscillation. a schmitt circuit is internally connected to this pin. an oscillation circuit is configured by connecting this pin and osc2 with a resistor (r) placed acro ss the connection (see figure below). make the wiring between this pin and the resistor as short as possible. if an external master oscillation clock is to be input, input the master os cillation clock to this pin. osc1 osc2 r r = 56 k ? (v dd = 4.5 to 5.5 v) ? osc2 output pin for rc oscillation. a schmitt circuit is internally connected to this pin. an oscillation circuit is configured by connecting this pin and osc1 with a resi stor (r) placed across the connection (see figure above). make the wiring between this pin and the resistor as short as possible. if an external master oscillation clock is to be input, leave this pin unconnected (open). ? reset reset signal input pin. a schmitt circuit is internally conn ected to this pin. the initial state can be set by pulling this pin to an ?l? level. refer to the ?output, i/o and re gister states in response to reset input? page for the initial states of each register and display. an internal pull-up resistor is connected to this pin. connecting an external capac itor enables power-on reset. ? test test signal input pin. connect this pin to v ss .
fedl9092-01 oki semiconductor ml9092-01/02/03/04 16/66 ? r0/c0 to r4/c4 (ml9092-01), r0 to r5 (ML9092-02/03), r0 to r4 (ml9092-04) key switch scan signal output pins. during the scan operation, ?l? level signals are output in the order of r0/c0, r1/c1, ..., r4/c4 (ml9092-01) or r0, r1, ..., r5 (ML9092-02 /03) or r0, r1, ..., r4 (ml9092-04). (refer to the description under the heading ?key scan? for details.) for the ml9092-01, r0 to r4 can be used as the output ports for the general-purpose port c depending on the input signal to the kps pin. ? c0/d0 to c4/d4 (ml9092-01), c0 to c3 (ML9092-02/03), c0 to c4 (ml9092-04) input pins that detect the key switch status. pull-up resi stors and a schmitt circuit are internally connected to these pins. assemble a key matrix between these pins and the r0/c0 to r4/c4 (ml9092-01) or r0 to r5 (ML9092-02/03) or r0 to r4 (ml9092-04) pins. for the ml9092-01, c0 to c4 can be used as the output ports for the general-purpose port d depending on the input signal to the kps pin. ? kps input pin that selects whether the r0/c0 to r4/c4 pins and c0/d0 to c4/d4 pins are used to detect the key switch status or whether they are used as the output pins for the general-purpose ports c and d. when this pin is pulled to a ?h? level, the r0/c0 to r4/c4 pins and c0/d0 to c4/d4 pins function as pins that detect the key switch status. when this pin is pulled to a ?l? level, it functions as the output pin for the general-purpose ports c and d. this pin must be fixed at either a ?h? or ?l? level. this pin is provided only for the ml9092-01. ? a, b input pins for encoder format rotary switches. a schmi tt circuit is internally connected to these pins. when turning the rotary switch clockwise, input to the a pin a signal more advancing in phase than the b pin. when turning the rotary switch counterclockwise, input to the b pin a signal more advancing in phase than the a pin. ? pa0 general-purpose port a output pin. this pin can output a current of ?15 ma. if this pin is used to drive an led, insert an external current limiting resistor in series with the led. if this pin is not used, leave it unconnected (open). ? pb0 to pb2 port b pins, which are used for pwm outputs. these pins are provided for the ml9092-01/04. any pins not to be used should be left unconnected (open). ? seg1 to seg60(56) segment signal output pins for lcd driving. any pins not to be used should be left unconnected (open). for the ml9092-01, only seg1 to seg56 apply. ? com1 to com10 common signal output pins for lcd driving. any pins not to be used should be left unconnected (open). ? v dd logic power supply connection pin. ? v ss power supply gnd connection pin. ? v in voltage doubler reference voltage input pin. a voltage twice that which is input to this pin is output to the v out pin. when the voltage doubler is not used, connect this pin to gnd. this pin is provided for the ml9092-01/02.
fedl9092-01 oki semiconductor ml9092-01/02/03/04 17/66 ? v s1 ? negative connection pin for the capacitor for the voltage doubler. connect a 4.7 f ( 30%) capacitor between this pin and the v c1 + pin. when the voltage doubler is not used, leave this pin unconnected (open). this pin is provided for the ml9092-01/02. ? v c1 + positive connection pin for the capacitor for the voltage doubler. connect a 4.7 f ( 30%) capacitor between this pin and the v s1 ? pin. when the voltage doubler is not used, leave this pin unconnected (open). this pin is provided for the ml9092-01/02. ? v out a voltage twice that which is input to the v in pin is output to this pin. connect a 4.7 f capacitor between this pin and the v ss pin. when the internal voltage doubler is not used, input the specified voltage to this pin from the outside. when built-in contrast adjustment (electronic vol ume) is used, leave the connection between this pin and the v 0 pin open. the lcd drive voltage will be output from the v 0 pin according to the contrast adjustment value. when built-in contrast adjustment is not used, connect this pin with the v 0 pin. this pin is provided for the ml9092-01/02. ? v 0, v 2 lcd bias pins. a bias dividing resistor is connected to these pins. these pins are provided for the ml9092-01/02/04. ? v hin lcd drive high voltage power supply connection pin. when built-in contrast adjustment (electronic volume) is used, input the lcd drive power supply voltage to this pin. the lcd drive voltage will be output from the v 0 pin according to the contrast adjustment value. when bu ilt-in contrast adjustment is not used, strap the v hin pin and v 0 pin outside the ic, and input the lcd drive voltage into both pins. this pin is provided for the ml9092-03/04. ? v 0, v 1, v 2, v 3 lcd bias pins. a bias dividing resistor is connected to these pins. when using a large-screen lcd, however, input the lcd bias voltage from outside the ic to these pins. this is applicable to the ml9092-03.
fedl9092-01 oki semiconductor ml9092-01/02/03/04 18/66 absolute maximum ratings parameter symbol condition rating unit applicable pins power supply voltage v dd ta = 25 c ?0.3 to +6.5 v v dd high power supply voltage v h ta = 25 c ?0.3 to +18.0 v v out , v hin bias voltage v bi ta = 25 c ?0.3 to v out (v hin ) + 0.3 v v c1 +, v 0 , v 1 , v 2 , v 3 voltage doubler reference voltage v in ta = 25 c ?0.3 to v dd + 0.3 v v in input voltage v i ta = 25 c ?0.3 to v dd + 0.3 v cs , cp , di/o, osc1, c0 to c3, c0 to c4, c0/d0 to c4/d4, kps, a, b, reset ta = 25 c ?20 to +3 ma pa0 output current i o ta = 25 c ?3 to +4 ma pb0 to pb2, r0/c0 to r4/c4, c0/d0 to c4/d4, r0 to r4, r0 to r5, di/o, kreq power dissipation p d ta = 85 c 190 mw ? storage temperature t stg ? ?55 to +150 c ? v ss is the reference voltage potential for all pins.
fedl9092-01 oki semiconductor ml9092-01/02/03/04 19/66 recommended operating conditions parameter symbol condition range unit applicable pins power supply voltage v dd ? 4.5 to 5.5 v v dd voltage doubler not used (contrast adjustment used) 4.5 to 16.5 v v out externally input power supply voltage 1 (applies to ml9092-01/02) v out voltage doubler not used & v out pin connected with v 0 pin (contrast adjustment not used) 4.0 to 16.5 v v out , v 0 contrast adjustment used 4.5 to 16.5 v v hin externally input power supply voltage 2 (applies to ml9092-03/04) v hin contrast adjustment not used (v hin pin connected with v 0 pin) 4.0 to 16.5 v v hin , v 0 bias voltage v 0 ? 4.0 to 16.5 v v 0 voltage doubler input voltage v in ? 0.8v dd to v dd v v in operating frequency of external clock f ope ? 210 to 445 khz osc1 oscillation resistance r v dd = 4.5 to 5.5 v 56 *1 k ? osc1, osc2 operating temperature t op ? ?40 to +85 c ? v ss is the reference voltage potential for all pins. *1: use a resistor with an accuracy of 2 % osc1 osc2 r
fedl9092-01 oki semiconductor ml9092-01/02/03/04 20/66 electrical characteristics oscillating frequency characteristics (v dd = 4.5 to 5.5 v, v out (v hin ) = 4.5 to 16.5 v, ta = ?40 to +85 c) parameter symbol condition min. typ. max. unit applicable pins oscillating frequency f osc 56 k ? (resistor with accuracy within 2%) 210 306 445 khz osc1, osc2 dc characteristics (v dd = 4.5 to 5.5 v, v out (v hin ) = 4.5 to 16.5 v, ta = ?40 to +85 c) parameter symbol condition min. ty p. max. unit applicable pins ?h? input voltage 1 v ih1 when input externally 0.85v dd ? ? v osc1 ?h? input voltage 2 v ih2 ? 0.85v dd ? ? v reset ?h? input voltage 3 v ih3 ? 0.85v dd ? ? v cp , a, b, c0?c3, c0/d0?c4/d4,c0?c4 cs , di/o ?h? input voltage 4 v ih4 ? 0.8v dd ? ? v kps ?l? input voltage 1 v il1 when input externally ? ? 0.15v dd v osc1 ?l? input voltage 2 v il2 ? ? ? 0.15v dd v reset ?l? input voltage 3 v il3 ? ? ? 0.15v dd v cp, a , b, cs , di/o, ?l? input voltage 4 v il4 ? ? ? 0.2v dd v kps ?l? input voltage 5 v il5 ? ? ? 0.23v dd v c0/d0?c4/d4,c0?c3, c0?c4 ?h? input current 1 i ih1 v i = v dd ? ? 10 a reset ?h? input current 2 i ih2 v i = v dd ? ? 10 a c0/d0?c4/d4, c0?c3, c0?c4 ?h? input current 3 i ih3 di/o = input mode, all ports = hiz, v i = v dd ? ? 10 a di/o, pa0, pb0?pb2, r0/c0?r4/c4, c0/d0?c4/d4 ?h? input current 4 i ih4 v i = v dd ? ? 1 a osc1, cs, cp , kps , a , b ?l? input current 1 i il1 v dd = 5 v, v i = 0 v ?0.1 ?0.05 ?0.02 ma reset ?l? input current 2 i il2 v dd = 5 v, v i = 0 v ?0.9 ?0.45 ?0.18 ma c0/d0?c4/d4, c0?c3,c0?c4 ?l? input current 3 i il3 di/o = input mode, all ports = hiz, v i = 0 v ?10 ? ? a di/o, pa0, pb0?pb2, r0/c0?r4/c4, c0/d?c4/d4 ?l? input current 4 i il4 v i = 0 v ?1 ? ? a osc1, cs, cp , kps, a, b
fedl9092-01 oki semiconductor ml9092-01/02/03/04 21/66 parameter symbol condition min. typ. max. unit applicable pins ?h? output voltage 1 v oh1 i o = ?0.4 ma v dd ? 0.4 ? ? v di/o, kreq ?h? output voltage 2 v oh2 i o = ?40 a 0.9v dd ? ? v osc2 ?h? output voltage 3 v oh3 i o = ?15 ma v dd ? 1.7 ? ? v pa0 ?h? output voltage 4 v oh4 i o = ?2 ma (when r0/c0? r4/c4 and c0/d0?c4/d4 are used as ports c and d) v dd ? 1.2 ? ? v only applies to ml9092-01. pb0?pb2, r0/c0?r4/c4, c0/d0?c4/d4 ?h? output voltage 5 v oh5 i o = ?50 a (when r0/c0? r4/c4 are used for key scanning) v dd ? 2.0 ? ? v r0/c0?r4/c4(-01), r0?r5 (-02, -03) r0?r4 (-04) ?l? output voltage 1 v ol1 i o = 0.4 ma ? ? 0.4 v di/o, kreq ?l? output voltage 2 v ol2 i o = 40 a ? ? 0.1v dd v osc2 ?l? output voltage 3 v ol3 i o = 1 ma (when r0/c0? r4/c4 and c0/d0?c4/d4 are used as ports c and d) ? ? 0.4 v pa0, pb0?pb2, c0/d0?c4/d4, r0/c0?r4/c4 ?l? output voltage 4 v ol4 i o = 2.7 ma (when r0/c0? r4/c4 are used for key scanning) ? ? 0.3 v r0/c?r4/c4 (-01), r0?r5 (-02, -03) r0?r4 (-04)
fedl9092-01 oki semiconductor ml9092-01/02/03/04 22/66 (v dd = 4.5 to 5.5 v, v out (v hin ) = 4.5 to 16.5 v, ta = ?40 to +85 c) parameter symbol condition min. typ. max. unit applicable pins v os0 i o = ?10 a v 0 ? 0.6 ? ? v v os1 i o = 10 a 2/4v 0 ? 0.6 ? 2/4v 0 + 0.6 v v os2 i o = 10 a 2/4v 0 ? 0.6 ? 2/4v 0 + 0.6 v segment output voltage 2 (1/5 bias) v os3 i o = +10 a ? ? v ss + 0.6 v seg1?seg56 (seg60 for ML9092-02/03 /04) v oc0 i o = ?10 a v 0 ? 0.3 ? ? v v oc1 i o = 10 a 3/4v 0 ? 0.3 ? 3/4v 0 + 0.3 v v oc2 i o = 10 a 1/4v 0 ? 0.3 ? 1/4v 0 + 0.3 v common output voltage 1 (1/4 bias) v oc3 i o = +10 a ? ? v ss + 0.3 v com1? com10 supply current 1 (applies to ml9092-01/02) i dd1 r = 56 k ? voltage doubler operating, no load *1 ? ? 0.6 ma v dd supply current 2 (applies to ml9092-01/02) i dd2 external clock = 445 khz voltage doubler operating, no load *2 ? ? 0.6 ma v dd supply current 3 (applies to ml9092-01/02) i vin external clock = 445 khz voltage doubler operating, no load *2 ? ? 2 ma v in supply current 4 (applies to ml9092-01/02) i vhin1 external clock = 445 khz voltage doubler not operating, no load *3 ? ? 1 ma v out supply current 5 (applies to ml9092-03/04) i dd3 r = 56 k ? no load *4 ? ? 0.6 ma v dd supply current 6 (applies to ml9092-03/04) i dd4 external clock = 445 khz no load *5 ? ? 0.6 ma v dd supply current 7 (applies to ml9092-03/04) i vhin2 external clock = 445 khz no load *5 ? ? 1 ma v hin supply current 8 (applies to ml9092-03/04) i dd5 r = 56 k ? voltage doubler not operating, no load *6 ? ? 100 a v dd *1: refer to the current measuring circuit 1. *2: refer to the current measuring circuit 2. *3: refer to the current measuring circuit 3. *4: refer to the current measuring circuit 4. *5: refer to the current measuring circuit 5. *6: refer to the current measuring circuit 6.
fedl9092-01 oki semiconductor ml9092-01/02/03/04 23/66 (v dd = 4.5 to 5.5 v, v out (v hin ) = 4.5 to 16.5 v, ta = ?40 to +85 c) parameter symbol condition min. typ. max. unit applicable pins voltage doubler voltage v db external clock = 210 khz v in = 0.8 v dd to v dd (*1) v in 1.9 ? 0.5 9.8 *3 v in 2 v v out v lcdmax v dd = 5 v, v out = 10 v (voltage doubler not operating, but voltage applied externally) contrast data = fh, no load 9.5 9.8 10 v lcd driving voltage when internal variable resistor is used v lcdmin v dd = 5 v, v out = 10 v (voltage doubler not operating, but voltage applied externally) contrast data = 0h, no load 6.7 7 7.3 v v 0 ? v ss lcd driving bias resistance lbr (*2) 5 9 14 k ? v 0 ? v ss *1 refer to the voltage doubler voltage measuring circuit. *3 v in = 5 v, ta = 25 c *2 lbr lbr v 0 v 2 v 1 v ss lbr lbr v 3
fedl9092-01 oki semiconductor ml9092-01/02/03/04 24/66 measuring circuits voltage doubler volt age measuring circuit current measuring circuit 1 current measuring circuit 2 *1: for ml9092-01, these are seg1?56, pb0? pb2, kps, c0/d0?c4/d4, and r0/c0?r4/c4. for ML9092-02, these are seg1?60, c0?c3, and r0?r5; pb0?pb2 and kps are not provided. v ss test pa0 seg1?seg56(60) com1?com10 *1 pb0?pb2 c0/d0?c4/d4 r0/c0?r4/c4 open v dd v in v c1 + v s1 ? c s c p di/o osc2 osc1 r eset v dd + ? open open v out v 2 4.7 f 30% + a i dd1 v ss test pa0 seg1?seg56(60) com1?com10 *1 pb0?pb2 c0/d0?c4/d4 r0/c0?r4/c4 open v dd v in c s c p di/o osc2 osc1 open r eset v dd + ? open open v 2 a i dd2 r = 56 k ? 2% 5.5 v 5.5 v 5.5 v 5.5 v v dd v dd f = 445 khz 30% 4.7 f f voltage is doubled (internal oscillation) voltage is doubled (external clock) a i vin v o v c1 + v s1 ? v o v out + 4.7 f 30% a b a b kps kps (c0?c3) (r0?r5) (c0?c3) (r0?r5) kreq open kreq open open open v ss voltage is doubled (1/4 bias) test pa0 seg1?seg56(60) com1?com10 *1 pb0?pb2 c0/d0?c4/d4 r0/c0?r4/c4 open v dd v in v c1 + v s1 ? v out v o v 2 c s c p di/o osc2 osc1 open f = 210 khz r ese t v dd v v db + v in 4.7 f 30% 100 a ? open open + v dd v dd 30% 4.7 f kps a b (c0?c3) (r0?r5) kreq open open
fedl9092-01 oki semiconductor ml9092-01/02/03/04 25/66 current measuring circuit 3 current measuring circuit 4 current measuring circuit 5 *1: for ml9092-01, these are seg1?56, pb0? pb2, kps, c0/d0?c4/d4, and r0/c0?r4/c4. for ML9092-02, these are seg1?60, c0?c3, and r0?r5; pb0?pb2 and kps are not provided. *2: for ml9092-03, these are c0?c3 and r0?r5; pb0?pb2 are not provided. for ml9092-04, these are c0?c4 and r0?r4; pb0?pb2 are provided. v ss test pa0 seg1?seg60 com1?com10 open v dd c s c p di/o osc2 osc1 r eset v dd open open *2 c0?c3 r0?r5 a i dd4 5.5 v v dd v o v hin v 2 v 1 v 3 open open a b kreq open f = 445 khz open a i vhin2 (c0?c4) (r0?r4) pb0?pb2 open external lcd voltage applied (external clock)?2 v ss test pa0 seg1?seg56(60) com1?com10 *1 pb0?pb2 c0/d0?c4/d4 r0/c0?r4/c4 open v dd v in v c1 + v s1 ? c s c p di/o osc2 osc1 r eset v dd open open v out v 2 v ss test pa0 seg1?seg60 com1?com10 pb0?pb2 c0?c3 r0?r5 open v dd c s c p di/o osc2 osc1 r eset v dd open open v 2 a i dd3 5.5 v 5.5 v v dd v dd external lcd voltage applied (external clock) i vhin1 v o v o v hin a open v 1 v 3 open open open r = 56 k ? 2% a b a b (r0?r5) (c0?c3) kreq open kreq open f = 445 khz open (c0?c4) (r0?r4) *2 open open kps external lcd voltage applied (internal oscillation)
fedl9092-01 oki semiconductor ml9092-01/02/03/04 26/66 current measuring circuit 6 *2: for ml9092-03, these are c0?c3 and r0?r5; pb0?pb2 are not provided. for ml9092-04, these are c0?c4 and r0?r4; pb0?pb2 are provided. 5.5 v v ss test pa0 seg1?seg60 com1?com10 *2 open v dd c s c p di/o osc2 osc1 r e set v dd open open i dd5 r = 56 k ? 2% v dd v hin v o a v 2 v 1 v 3 open open a b c0?c3 r0?r5 kreq open (c0?c4) (r0?r4) pb0?pb2 open external lcd voltage applied (internal oscillation)
fedl9092-01 oki semiconductor ml9092-01/02/03/04 27/66 switching characteristics (v dd = 4.5 to 5.5 v, v out (v hin ) = 4.5 to 16.5 v, ta = ?40 to +85 c) parameter symbol condition min. max. unit cp clock cycle time t sys ? 500 ? ns cp ?h ? pulse width t wh ? 200 ? ns cp ?l ? pulse width t wl ? 200 ? ns cs ?h ? pulse width t wch ? 100 ? ns cp clock rise/fall time t r , t f ? ? 50 ns cs setup time t csu ? 30 ? ns cs hold time t chd ? 150 ? ns di/o setup time t dsu ? 50 ? ns di/o hold time t dhd ? 50 ? ns di/o output delay time t dod cl = 50 pf ? 100 ns di/o output off delay time t doff cl = 50 pf ? 100 ns reset pulse width t wre ? 2 ? s external clock cycle time t ses ? 1612 3389 ns external clock ?h? pulse width t weh ? 645 ? ns external clock ?l? pulse width t wel ? 645 ? ns external clock rise/fall time t re , t fe ? ? 50 ns key scan characteristics (v dd = 4.5 to 5.5 v, v out (v hin ) = 4.5 to 16.5 v, ta = ?40 to +85 c) register setting oscillation frequency parameter symbol kt dividing ratio 210 khz 306khz 445 khz unit 0 1/1536 7.3 5.0 3.5 key scan period t scn 1 1/3072 14.6 10.0 6.9 ms frame frequency, pwm frequency, and vo ltage doubler frequency characteristics (v dd = 4.5 to 5.5 v, v out (v hin ) = 4.5 to 16.5 v, ta = ?40 to +85 c) oscillation frequency model parameter symbol display duty dividing ratio 210 khz 306 khz 445 khz unit 1/8 1/2560 82 120 174 1/9 1/2520 83 121 177 ml9092- 01/02/03/04 frame frequency frm 1/10 1/2560 82 120 174 ml9092- 01/04 pwm frequency pwm ? 1/1020 205 300 436 ml9092- 01/02 voltage doubler frequency ? ? 1/64 3281 4781 6953 hz
fedl9092-01 oki semiconductor ml9092-01/02/03/04 28/66 switching characteristics of rotary switch (v dd = 4.5 to 5.5 v, v out (v hin ) = 4.5 to 16.5 v, ta = ?40 to +85 c) parameter symbol condition min. typ. max. unit phase recognition time (a to b) t saw 950 ? ? s phase recognition time (b to a) t sbw 950 ? ? s phase input fixed time t ab r = 56 k ? 2%, 950 ? ? s
fedl9092-01 oki semiconductor ml9092-01/02/03/04 29/66 clock synchronous serial interface timing diagrams clock synchronous serial interface input timing clock synchronous se rial interface input output timing reset timing external clock cp c s di/o t csu t sys t dhd t wl t wh t r t f t chd t wch ? v ih3 ? v ih3 ? v ih3 ? v il3 ? v il3 t dsu ? v il3 cp c s di/o t csu t sys t dhd t dod t doff t wl t wh t r t f t chd t wch ? v ih3 ? v il3 ? v ih3 8th clock v ih3 v ih3 v il3 v oh1 v ol1 v oh1 v ol1 hiz v il3 ? v il3 1st clock t dsu 9th clock r ese t t wre ? v il2 osc1 t ses t wel t fe t weh t re ? v ih1 ? v il1
fedl9092-01 oki semiconductor ml9092-01/02/03/04 30/66 key scan timing frame frequency 1/frm 1/frm ? v 0 ? v ss ? v 3 ? v 1 com1 pwm output frequency for port b (applies to ml9092-01/04) rotary switch input timing rn t scn ?v dd ?v ss pb0 pb1 pb2 1/pwm t saw t saw t sbw t sbw t ab t ab t ab t ab a b
fedl9092-01 oki semiconductor ml9092-01/02/03/04 31/66 instruction code list (ml9092-01) instruction code data no. instruction fixed bit r/w register no. description d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0 ke y scan re g ister read 1 1 1 0 0 0 0 0 st2 st1 st0 s4 s3 s2 s1 s0 reads scan read timing bits (st0 to st2) and key scan data (s0 to s4) of the key scan register. 1 display data ram write 1 1 0 0 0 0 0 1 d7 d6 d5 d4 d3 d2 d1 d0 1 display data ram read 1 1 1 0 0 0 0 1 d7 d6 d5 d4 d3 d2 d1 d0 2 x address register set 1 1 0 0 0 0 1 0 ? ? ? ? x3 x2 x1 x0 sets the x address (x0 to x3) of the display data ram. 3 y address register set 1 1 0 0 0 0 1 1 ? ? ? ? y3 y2 y1 y0 sets the y address (y0 to y3) of the display data ram. 4 port register a set 1 1 0 0 0 1 0 0 ? ? ? ? ? ? ? pta0 controls the output of the general-purpose port a (pta0). 5 port register b set 1 1 0 0 0 1 0 1 ? ? ? ? ? ptb2 ptb1 ptb0 controls the output of the general-purpose port b (ptb0 to ptb2 ) . 6 port register c set 1 1 0 0 0 1 1 0 ? ? ? ptc4 ptc3 ptc2 ptc1 ptc0 7 port register d set 1 1 0 0 0 1 1 1 ? ? ? ptd4 ptd3 ptd2 ptd1 ptd0 8 control register 1 set 1 1 0 0 1 0 0 0 inc wls kt shl be pe dty1 dty0 sets the address increment x or y direction (inc), displa y data word length (wls), key scan time (kt), common driver shift direction (shl), voltage doubler control (be), port control (pe), and display duty (dty0, dty1). 9 control register 2 set 1 1 0 0 1 0 0 1 0 0 0 0 0 0 0 disp sets display on/off (disp). a rotary encoder read 1 1 1 0 1 0 1 0 q4 q4 q4 q4 q4 q3 q2 q1 reads the counter bits (q1 to q4) of the rotary encoder. b contrast adj set 1 1 0 0 1 0 1 1 ? ? ? ? ct3 ct2 ct1 ct0 sets contrast adjustment values with the contrast ad j ustment bits ( ct0 to ct3 ) . c pwm0 register set 1 1 0 0 1 1 0 0 pw07 pw06 pw05 pw04 pw03 pw02 pw01 pw00 sets the pulse width to be output from general-purpose port b (ptb0) with the bits (pw00 to pw07) of pwm0. d pwm1 register set 1 1 0 0 1 1 0 1 pw17 pw16 pw15 pw14 pw13 pw12 pw11 pw10 e pwm2 register set 1 1 0 0 1 1 1 0 pw27 pw26 pw25 pw24 pw23 pw22 pw21 pw20 f test register set 1 1 0 0 1 1 1 1 ? ? ? t5 t4 t3 t2 t1 test instruction exclusively used by manufacturer (t1 to t5). customers must not use this instruction. notes: r/w : read/write select bit 1:read, 0: write st0 to st2 : key scan read count display bits s0 to s4 : key scan data d0 to d7 : write or read data of the display data ram x0 to x3 : x addresses of the display data ram y0 to y3 : y addresses of the display data ram pta0 : port a data ptb0 to ptb2 : port b output cont rol 1: output enable, 0: fixed at ?l? ptc0 to ptc4 : port c data ptd0 to ptd4 : port d data inc : display data ram address increment. 1: x direction, 0: y direction wls : word length select bit 1: 6 bits, 0: 8 bits kt : key scan period select bit 1: 10 ms, 0: 0.5 ms shl : common driver shift direction select bit 1: com10 com1, 0: com1 com10 be : voltage doubler control bit 1: voltage doubler enable 0: voltage doubler disable pe : port enable/disable select bit 1: all ports enable 0: all ports go into high impedance for output dty0, dty1 : display duty select bits (1/8, 1/9, 1/10) disp : display on/off select bit 1: display on, 0: display off q1 to q4 : rotary encoder switch count bits (2?s complement) ct0 to ct3 : contrast adjustment bit pw00 to pw07 : pwm0 setting bits pw10 to pw17 : pwm1 setting bits pw20 to pw2 : pwm2 setting bits t1 to t5 : bits for test instruction. customers should not access these bits. ? : don?t care writes display data (d0 to d7) in the display data ram after setting the x address of y address. reads display data (d0 to d7) from the display data ram after setting the x address of y address. controls the output of the general-purpose port c (ptc0 to ptc4). controls the output of the general-purpose port d (ptd0 to ptd4 ) . sets the pulse width to be output from general-purpose port b (ptb1) with the bits (pw10 to pw17) of pwm1. sets the pulse width to be output from general-purpose port b (ptb2) with the bits (pw20 to pw27) of pwm2.
fedl9092-01 oki semiconductor ml9092-01/02/03/04 32/66 instruction code list (ML9092-02/03) instruction code data no. instruction fixed bit r/w register no. description d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0 key scan register read 1 1 1 0 0 0 0 0 st2 st1 st0 0 s3 s2 s1 s0 reads scan read timing bits (st0 to st2) and key scan data (s0 to s4) of the key scan register. 1 display data ram write 1 1 0 0 0 0 0 1 d7 d6 d5 d4 d3 d2 d1 d0 1 display data ram read 1 1 1 0 0 0 0 1 d7 d6 d5 d4 d3 d2 d1 d0 2 x address register set 1 1 0 0 0 0 1 0 ? ? ? ? x3 x2 x1 x0 sets the x address (x0 to x3) of the display data ram. 3 y address register set 1 1 0 0 0 0 1 1 ? ? ? ? y3 y2 y1 y0 sets the y address (y0 to y3) of the display data ram. 4 port register a set 1 1 0 0 0 1 0 0 ? ? ? ? ? ? ? pta0 controls the output of the general-purpose port a (pta0). 8 control register 1 set 1 1 0 0 1 0 0 0 inc wls kt shl (be) pe dty1 dty0 sets the address increment x or y direction (inc), displa y data word length (wls), key scan time (kt), common driver shift direction (shl), voltage doubler control (be) (only applies to ML9092-02), port control (pe), and displa y dut y ( dty0, dty1 ) . 9 control register 2 set 1 1 0 0 1 0 0 1 0 0 0 0 0 0 (stb) disp sets or releases standby mode (only applies to ml9092- 03) and also sets display on/off (disp). a rotary encoder read 1 1 1 0 1 0 1 0 q4 q4 q4 q4 q4 q3 q2 q1 reads the counter bits (q1 to q4) of the rotary encoder. b contrast adj set 1 1 0 0 1 0 1 1 ? ? ? ? ct3 ct2 ct1 ct0 sets contrast adjustment values with the contrast ad j ustment bits ( ct0 to ct3 ) . f test register set 1 1 0 0 1 1 1 1 ? ? ? t5 t4 t3 t2 t1 test instruction exclusively used by manufacturer (t1 to t5). customers should not use this instruction. writes display data (d0 to d7) in the display data ram after setting the x address of y address. reads display data (d0 to d7) from the display data ram after setting the x address of y address. notes: r/w : read/write select bit 1:read, 0: write st0 to st2 : key scan read count display bits s0 to s3 : key scan data d0 to d7 : write or read data of the display data ram x0 to x3 : x addresses of the display data ram y0 to y3 : y addresses of the display data ram pta0 : port a data inc : display data ram address increment. 1: x direction, 0: y direction wls : word length select bit 1: 6 bits, 0: 8 bits kt : key scan period select bit 1: 10 ms, 0: 0.5 ms shl : common driver shift direction select bit 1: com10 com1, 0: com1 com10 be (only applies to ML9092-02) : voltage doubler control bit 1: voltage doubler enable 0: voltage doubler disable pe : port enable/disable select bit 1: all ports enable 0: all ports go into high impedance for output dty0, dty1 : display duty select bits (1/8, 1/9, 1/10) disp : display on/off select bit 1: display on, 0: display off q1 to q4 : rotary encoder switch count bits (2?s complement) ct0 to ct3 : contrast adjustment bit t1 to t5 : bits for test instruction. customers should not access these bits. ? : don?t care stb (only applies to ml9092-03) : standby mode/normal mode select bit 1: standby mode, 0: normal mode
fedl9092-01 oki semiconductor ml9092-01/02/03/04 33/66 instruction code list (ml9092-04) instruction code data no. instruction fixed bit r/w register no. description d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0 ke y scan re g ister read 1 1 1 0 0 0 0 0 st2 st1 st0 s4 s3 s2 s1 s0 reads scan read timing bits (st0 to st2) and key scan data (s0 to s4) of the key scan register. 1 display data ram write 1 1 0 0 0 0 0 1 d7 d6 d5 d4 d3 d2 d1 d0 1 display data ram read 1 1 1 0 0 0 0 1 d7 d6 d5 d4 d3 d2 d1 d0 2 x address register set 1 1 0 0 0 0 1 0 ? ? ? ? x3 x2 x1 x0 sets the x address (x0 to x3) of the display data ram. 3 y address register set 1 1 0 0 0 0 1 1 ? ? ? ? y3 y2 y1 y0 sets the y address (y0 to y3) of the display data ram. 4 port register a set 1 1 0 0 0 1 0 0 ? ? ? ? ? ? ? pta0 controls the output of the general-purpose port a (pta0). 5 port register b set 1 1 0 0 0 1 0 1 ? ? ? ? ? ptb2 ptb1 ptb0 controls the output of the general-purpose port b (ptb0 to ptb2 ) . reads the counter bits (q1 to q4) of the rotary encoder. writes display data (d0 to d7) in the display data ram after setting the x address of y address. reads display data (d0 to d7) from the display data ram after setting the x address of y address. 8 control register 1 set 1 1 0 0 1 0 0 0 inc wls kt shl ? pe dty1 dty0 sets the address increment x or y direction (inc), displa y data word length (wls), key scan time (kt), common driver shift direction (shl), port control (pe), and display duty (dty0, dty1). 9 control register 2 set 1 1 0 0 1 0 0 1 0 0 0 0 0 0 stb disp sets or releases standby mode and also sets display on/off (disp). a rotary encoder read 1 1 1 0 1 0 1 0 q4 q4 q4 q4 q4 q3 q2 q1 b contrast adj set 1 1 0 0 1 0 1 1 ? ? ? ? ct3 ct2 ct1 ct0 sets contrast adjustment values with the contrast ad j ustment bits ( ct0 to ct3 ) . c pwm0 register set 1 1 0 0 1 1 0 0 pw07 pw06 pw05 pw04 pw03 pw02 pw01 pw00 sets the pulse width to be output from general-purpose port b (ptb0) with the bits (pw00 to pw07) of pwm0. d pwm1 register set 1 1 0 0 1 1 0 1 pw17 pw16 pw15 pw14 pw13 pw12 pw11 pw10 e pwm2 register set 1 1 0 0 1 1 1 0 pw27 pw26 pw25 pw24 pw23 pw22 pw21 pw20 f test register set 1 1 0 0 1 1 1 1 ? ? ? t5 t4 t3 t2 t1 test instruction exclusively used by manufacturer (t1 to t5). customers must not use this instruction. sets the pulse width to be output from general-purpose port b (ptb1) with the bits (pw10 to pw17) of pwm1. sets the pulse width to be output from general-purpose port b (ptb2) with the bits (pw20 to pw27) of pwm2. notes: r/w : read/write select bit 1:read, 0: write st0 to st2 : key scan read count display bits s0 to s4 : key scan data d0 to d7 : write or read data of the display data ram x0 to x3 : x addresses of the display data ram y0 to y3 : y addresses of the display data ram pta0 : port a data ptb0 to ptb2 : port b output cont rol 1: output enable, 0: fixed at ?l? inc : display data ram address increment. 1: x direction, 0: y direction wls : word length select bit 1: 6 bits, 0: 8 bits kt : key scan period select bit 1: 10 ms, 0: 0.5 ms shl : common driver shift direction select bit 1: com10 com1, 0: com1 com10 pe : port enable/disable select bit 1: all ports enable 0: all ports go into high impedance for output dty0, dty1 : display duty select bits (1/8, 1/9, 1/10) disp : display on/off select bit 1: display on, 0: display off q1 to q4 : rotary encoder switch count bits (2?s complement) ct0 to ct3 : contrast adjustment bit pw00 to pw07 : pwm0 setting bits pw10 to pw17 : pwm1 setting bits pw20 to pw2 : pwm2 setting bits t1 to t5 : bits for test instruction. customers should not access these bits. ? : don?t care stb : standby mode/normal mode select bit 1: standby mode, 0: normal mode
fedl9092-01 oki semiconductor ml9092-01/02/03/04 34/66 clock synchronous serial transfer example (write) c s cp transfer start transfer complete di/o register bits r/w d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 ?1? ?1? 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 data instruction code clock synchronous serial continuous data transf er example (write: example of display data ram write) c s cp transfer start transfer complete di/o 1 2 7 8 9 10 15 16 17 18 23 24 41 42 47 48 instruction code *1 data 1 data 2 data 5 *1: be sure to write data in 8 bits. if the cs signal falls when data input operation in 8 bits is not complete, the last 8-bit data write is invalid . (the previously written data is valid.)
fedl9092-01 oki semiconductor ml9092-01/02/03/04 35/66 clock synchronous serial continuo us data transfer example (read) c s cp transfer start transfer complete di/o 1 2 8 9 11 10 15 16 17 18 23 24 41 42 47 48 instruction code read data1 read data2 read data5 output state input state *2 *2: a reading state appears only when the r/w bit is ?1 ?. the read data is valid only when the register is set to key scan read mode, rotary encoder read mode or display data read mode. otherwise, the read data is invalid (undefined data will be read out).
fedl9092-01 oki semiconductor ml9092-01/02/03/04 36/66 output pin, i/o pin and register states when reset is input pin and register states while the reset input is pulled to a ?l? level are listed below. output pin, i/o pin state di/o input state kreq ?l? (v ss ) osc2 oscillating state r0/c0 to r4/c4 (when these pins are used for key scanning in ml9092-01); r0 to r5 (ML9092-02/03); r0 tor4 (ml9092-04) ?l? (v ss ) r0/c0 to r4/c4 (when these pins are used as port c outputs in ml9092-01) high impedance c0/d0 to c4/d4 (when these pins are used as port d outputs in ml9092-01) high impedance (any pull-up resistors are turned off) pa0 high impedance pb0 to pb2 (ml9092-01/04) high impedance seg1 to seg56 (ml9092-01); seg1 to seg60 (ML9092-02/03/04) v ss com1 to com10 v ss register state key scan register reset to ?0? display data register di splay data is retained x address register reset to ?0? y address register reset to ?0? port a register reset to ?0? port b register (ml9092-01/04) reset to ?0? port c register (when kps = ?0? in ml9092-01) reset to ?0? port d register (when kps = ?0? in ml9092-01) reset to ?0? control register 1 bits inc and kt are set to ?1?. bits wls, shl, pe, dty1 an d dty0 are reset to ?0?. control register 2 display off, normal mode (standby mode is released) rotary encoder read re gister reset to ?0? contrast adj register set to ?f? pwm0 register (for ml9092-01/04) reset to ?0? pwm1 register (for ml9092-01/04) reset to ?0? pwm2 register (for ml9092-01/04) reset to ?0?
fedl9092-01 oki semiconductor ml9092-01/02/03/04 37/66 power-on reset the capacitance of an external cap acitor that is connected to the reset pin must be c rst [ f] 12.5 t r [s], where t r is the rise time taken until the power supply voltage to be supplied to the ml9092-01/02/03/04 reaches 0.9v dd (4.5 v) from 0.1v dd , and c rst is the capacitance of an exte rnal capacitor connected to the reset pin. (for example, if t r = 10 [ms], then c rst 0. 125 [ f]) the pulse width when an external reset signal is input should be t r or more. set an instruction at least 10 s after the reset signal reaches 0.85v dd or more. thereafter, this ic is accessible. t r 0.1v dd v dd 0.9v dd (4.5 v) recommended power supply voltage (5 v) 0.85v dd reset 10 s or more accessible time
fedl9092-01 oki semiconductor ml9092-01/02/03/04 38/66 serial interface operation ? instruction code a register that transfers display data, key scan data, etc. acc ording to the content of the instruction code is selected (see below). d7 d6 d5 d4 d3 d2 d1 d0 ?1? ?1? r/w register number (1) d7, d6 (fixed at ?1?) when selecting the start byte register, always write a ?1? to bits d7 and d6. (2) d5 (r/w) (read mode/write mode select bit) 1: read mode is selected 0: write mode is selected (3) d4 to d0 (register number) the correspondence between the start byte contents and the registers and display data ram is shown in the table below. d7 d6 d5 d4 d3 d2 d1 d0 register name 1 1 0 1 0 0 0 0 key scan register 1 1 1 1/0 0 0 0 1 display data ram 1 1 0 0 0 0 1 0 x address register 1 1 0 0 0 0 1 1 y address register 1 1 0 0 0 1 0 0 port a register 1 1 0 0 0 1 0 1 port b register 1 1 0 0 0 1 1 0 port c register 1 1 0 0 0 1 1 1 port d register 1 1 0 0 1 0 0 0 control register1 1 1 0 0 1 0 0 1 control register 2 1 1 1 0 1 0 1 0 rotary encoder register 1 1 0 0 1 0 1 1 contrast adj register 1 1 0 0 1 1 0 0 pwm0 register 1 1 0 0 1 1 0 1 pwm1 register 1 1 0 0 1 1 1 0 pwm2 register
fedl9092-01 oki semiconductor ml9092-01/02/03/04 39/66 description of the data section in instructions ? key scan register (kr)?read (for ml9092-01/04) d7 d6 d5 d4 d3 d2 d1 d0 st2 st1 st0 s4 s3 s2 s1 s0 (1) d7 to d5 (st2 to st0) (key scan read count display bits) 25-bit key scan data is divided into 5 groups and read. the read count is indicated by bits st2 to st0. every time key scan data is read, these bits are automatica lly incremented over the range of ?000? to ?100?. after counting to ?100?, this counter is reset to ?000? and then again incremented from ?000?, thereafter repeating this cycle. if the cs signal is risen up during the cycle of counting, the scan read counter bits are returned to ?000?. if the reset pin is pulled to a ?l? level, these bits are reset to ?0?. (2) d4 to d0 (s4 to s0) (key scan read data bits) these bits are read as 25-bit serial data that expresses the key switch status (1 = on, 0 = off). data is divided into 5 groups and read. (for the read order, refer to the description below.) the read count is indicated by bits st2 to st0. the correspondence between the scan read count data, key scan data and key matrix switches is shown below. if the reset pin is pulled to a ?l? level, these bits are reset to ?0?. st2 st1 st0 s4 s3 s2 s1 s0 0 0 0 sw04 sw03 sw02 sw01 sw00 r0 0 0 1 sw14 sw13 sw12 sw11 sw10 r1 0 1 0 sw24 sw23 sw22 sw21 sw20 r2 0 1 1 sw34 sw33 sw32 sw31 sw30 r3 1 0 0 sw44 sw43 sw42 sw41 sw40 r4 note: sw00 to sw44 indicate the corresponding switches in figure 1.
fedl9092-01 oki semiconductor ml9092-01/02/03/04 40/66 c0 sw00 c1 sw01 c2 sw02 c3 sw03 c4 r0/c0 r0 sw04 sw10 sw11 sw12 sw13 sw14 sw20 sw21 sw22 sw23 sw24 sw30 sw31 sw32 sw33 sw34 sw40 sw41 sw42 sw43 sw44 ml9092-01, -04 r1/c1 r1 r3/c3 r3 r4/c4 r4 r2/c2 r2 c0/d0 c1/d1 c4/d4 c2/d2 c3/d3 figure 1 (note) to recognize simultaneous depression of three or more key switches, add a diode in series to each key. cm/dm cm rn/cn rn rn + 1 / c n + 1 rn+1 connection with diodes
fedl9092-01 oki semiconductor ml9092-01/02/03/04 41/66 ? key scan register (kr)?read (for ML9092-02/03) d7 d6 d5 d4 d3 d2 d1 d0 st2 st1 st0 0 s3 s2 s1 s0 (1) d7 to d5 (st2 to st0) (key scan read count display bits) 24-bit key scan data is divided into 6 groups and read. the read count is indicated by bits st2 to st0. every time key scan data is read, these bits are automatica lly incremented over the range of ?000? to ?101?. after counting to ?101?, this counter is reset to ?000? and then again incremented from ?000?, thereafter repeating this cycle. if the cs signal is risen up during the cycle of counting, the scan read counter bits are returned to ?000?. if the reset pin is pulled to a ?l? level, these bits are reset to ?0?. (2) d3 to d0 (s3 to s0) (key scan read data bits) these bits are read as 24-bit serial data that expresses the key switch status (1 = on, 0 = off). data is divided into 6 groups and read. (for the read order, refer to the description below.) the read count is indicated by bits st2 to st0. the correspondence between the scan read count data, key scan data and key matrix switches is shown below. if the reset pin is pulled to a ?l? level, these bits are reset to ?0?. st2 st1 st0 s4 s3 s2 s1 s0 0 0 0 0 sw03 sw02 sw01 sw00 r0 0 0 1 0 sw13 sw12 sw11 sw10 r1 0 1 0 0 sw23 sw22 sw21 sw20 r2 0 1 1 0 sw33 sw32 sw31 sw30 r3 1 0 0 0 sw43 sw42 sw41 sw40 r4 1 0 1 0 sw53 sw52 sw51 sw50 r5 note: sw00 to sw53 indicate the corresponding switches in figure 2.
fedl9092-01 oki semiconductor ml9092-01/02/03/04 42/66 sw00 sw01 sw02 sw03 sw10 sw11 sw12 sw13 sw20 sw21 sw22 sw23 sw30 sw31 sw32 sw33 sw40 sw41 sw42 sw43 ML9092-02/03 sw50 sw51 sw52 sw53 c0 c1 r0 c3 c2 r1 r2 r3 r4 r5 figure 2 (note) to recognize simultaneous depression of three or more key switches, add a diode in series to each key. rn cm rn+1 connection with diodes
fedl9092-01 oki semiconductor ml9092-01/02/03/04 43/66 key scan the key scanning starts when a key switch is pressed on and ends after all key switches are detected to be off. after the key switch is turned on, when the same key is pressed for two cycles or more, the level of the kreq signal changes from a ?l? to ?h? level. in the same ma nner, the level of the kreq signal changes from ?h? to ?l? two cycles after all ke y switches are turned off. this signal can be used as a flag. to use it as a flag, start key-scan reading when the kreq signal has changed from ?l? to ?h.? while the kreq signal is at a ?h? level, carry out key-scan reading periodica lly. carry out key scan reading also when the kreq signal has changed from ?h? to ?l?. the kreq signal (the kreq signal that is sent when the key switch is turned on) is re set when all key switches are detected to be off or when a ?l? level is applied to the reset pin. scanning stops key switch off key data reading starts key switch on. scanning starts. kreq key switch r0/c0 r1/c1 r2/c2 r3/c3 r4/c4 notes: 1. even when the kreq signal changes from ?l? to ?h?, chattering for more than one key scan cycle is not absorbed. this should be handled by multiple data reads by software. 2. how simultaneous depression of two keys is processed should be handled by software. 3. when three or more key switches are pressed at the same time, the device may recognize that key(s) that has not been actually pressed has been pressed. therefore, to recognize simultaneous depression of three or more key switches, add a diode in series to each key (see figures 1 and 2). to ignore simultaneous depression of three or more key switches, a program may be required to ignore all key data which contains thr ee or more consecutive ?1? values.
fedl9092-01 oki semiconductor ml9092-01/02/03/04 44/66 ? display data ram (dram) read/write d7 d6 d5 d4 d3 d2 d1 d0 8-bit data 0 0 6-bit data the display data ram read/write instruction writes and re ads display data to and from the liquid crystal display ram. data that is input to the address set by the x and y ad dress registers is written to or read from this register. the bit length of display data can be selected by the wls bit of control register 1. if 6-bit data has been selected, writing to d7 and d6 is invalid, and if read, their values will always be ?0?. d7 is the msb (d5 in the case of 6-bit data) and d0 is the lsb. the x address and y address should be set immediately befo re writing or reading display data (either x address or y address may be set first). however, in the case of su ccessive writings or readings, only one-time settings of x address and y address are required immediately before the writing or reading, in which case x address and y address are automatically incremented every time data is written or read (see the description under the heading ?x ? y address counter auto increment.? the contents of this register will not change even if the reset pin is pulled to a ?l? level. ? x address register (xad) set d7 d6 d5 d4 d3 d2 d1 d0 ? xad ?: don?t care the x address register set instructions sets the x address for the liquid crystal display ram. the address setting range is 0 to 7 (00h to 07h) when 8-bit data is selected with the wls bit (bit d6) of the control register 1 (wls = ?0?). in this case, this register st arts incrementing the x addre ss from the set value each time ram is read or written. when the count value of this register returns to 0 from the maximum value 7, the y address is automatically incremented as well. thereafter, the y address is counted in a loop fashion from 0 to 7. the address setting range is 0 to 9 (00h to 09h) when 6-bit da ta is selected (wls = ?1?). in this case this register starts incrementing the x address from the set value. when the count value of this register returns to 0 from the maximum value 9, the y address is automatically incremented as well. thereafter, the y address loops from 0 to 9. proper operation is not guaranteed if va lues outside this range are set. writing to bits d7 through d4 is invalid. if the reset pin is pulled to a ?l? level, these bits are reset to ?0?. ? y address register (yad) set d7 d6 d5 d4 d3 d2 d1 d0 ? yad ?: don?t care the y address register set instruction sets a y address of ram for the liquid crystal display. the y address setting range varies accordi ng to the setting of the dt y bits (bits d1 and d0) of the control register 1 (described later). the relation between the internal ram areas and the display ram areas is sh own in the table below. ram areas that are not displayed can be used as data ram areas. this register starts incrementing the y address from th e set value each time ram is read or written. when the register count returns to 0 from the maximum value (09h), the x address is also incremented automatically. thereafter, the y address is counted in a loop fashion as shown in the table below. however, if ram areas that are not displayed are used, the x addr ess is not incremented automatically.
fedl9092-01 oki semiconductor ml9092-01/02/03/04 45/66 duty y register setting range and loop range invalid address setting range 1/8 0 to 7 (00h to 07h) 0 to 7 (00h to 07h) 1/9 0 to 8 (00h to 08h) 0 to 8 (00h to 08h) 1/10 0 to 9 (00h to 09h) 0 to 9 (00h to 09h) this register is reset to ?0? when the reset pin is made low. ? port register a (pta) set d7 d6 d5 d4 d3 d2 d1 d0 ? pta ?: don?t care the port register a set instruction sets the output of port a. when the pta bit is set to ?1?, a ?h? level is output from the pa0 pin of general purpose port a. in the same way, when the pta bit is set to ?0?, a ?l? level is output from the pa0 pin. if the reset pin is pulled to a ?l? level, the pe bit (bit d2) of the control register is reset to ?0?, th is register is reset to ?0?, and the pa0 pin goes to high impedance. after the reset state is released, if the pta bit of this register is set to ?1? or ?0? and then the pe bit is set to ?1?, the pa0 pin is released from its high impedance state and a ?h ? or ?l? level that corresponds to the set status of the pta bit, is output from the pa0 pin. ? port register b (ptb) set d7 d6 d5 d4 d3 d2 d1 d0 ? ptb2 ptb1 ptb0 ?: don?t care the port register b set instruction sets the output of port b. (applies to the ml9092-01/04.) when each bit of ptb0 to ptb2 is set to ?1?, the pwm si gnal set in the pwm0 to pwm2 registers is output from each of the pb0 to pb2 pins of the general purpose port b. in the same way, when each bit of ptb0 to ptb2 is set to ?0?, each of the pb0 to pb2 pins are pulled to a ?l? level. if the reset pin is pulled to a ?l? level, the pe bit (bit d2) of the control register is reset to ?0?, this regist er is reset to ?0?, and the pb0 to pb2 pins go to high impedance. after the reset state is released, if the a pwm value is set in the pwm0 to pwm2 registers and then the pe bit is set to ?1?, the pb0 to pb2 registers are released from th eir high impedance state and a pwm waveform is output.
fedl9092-01 oki semiconductor ml9092-01/02/03/04 46/66 ? port register c (ptc) set d7 d6 d5 d4 d3 d2 d1 d0 ? ? ? ptc4 ptc3 ptc2 ptc1 ptc0 ?: don?t care the port register c set instruction sets the output of port c. (applies to the ml9092-01 only.) this register is enabled when a ?l? le vel is applied to the kps pin of ml9092-01 and the r0/c0 to r4/c4 pins are set as port c. when each bit of ptc4 to ptc0 is set to ?1?, a ?h? leve l is output from each of the r4/c4 to r0/c0 pins of the general purpose port c. in the same way, when each bit of ptc4 to ptc0 is set to ?0?, a ?h? level is output from each of the r4/c4 to r0/c0 pins. if the reset pin is pulled to a ?l? level, the pe bit (bit d2) of the control register is reset to ?0?, this register is reset to ?0?, and the r4/c4 to r0/c0 pins go to high impedance. after the reset state is released, if the ptc4 to ptc0 bits of this register are set to ?1? or ?0? and then the pe bit is set to ?1?, the r4/c4 to r0/c0 pins are released from its high impedan ce state and a ?h? or ?l? level that corresponds to the set status of each bit of ptc4 to ptc0, is output from the r4/c4 to r0/c0 pins. ? port register d (ptd) set d7 d6 d5 d4 d3 d2 d1 d0 ? ? ? ptd4 ptd3 ptd2 ptd1 ptd0 ?: don?t care the port register d set instruction sets the output of port d. (applies to the ml9092-01 only.) this register is enabled when a ?l? level is applied to the kps pin of ml9092-01 and the c0/d0 to c4/d4 pins are set as port c. when each bit of ptd4 to ptd0 is set to ?1?, a ?h? leve l is output from each of the c4/d4 to c0/d0 pins of the general purpose port d. in the same way, when each bit of ptd4 to ptd0 is set to ?0?, a ?h? level is output from each of the c4/d4 to c0/d0 pins. if the reset pin is pulled to a ?l? level, the pe bit (bit d2) of the control register is reset to ?0?, this register is reset to ?0?, and the c4/d4 to c0/d0 pins go to high impedance. after the reset state is released, if the ptd4 to ptd0 bits of this register are set to ?1? or ?0? and then the pe bit is set to ?1?, the c4/d4 to c0/d0 pins are released from its high impedance state and a ?h? or ?l? level that corresponds to the set status of each bit of ptd4 to ptd0, is output from the c4/d4 to c0/d0 pins. ? control register 1 (fcr1) d7 d6 d5 d4 d3 d2 d1 d0 inc wls kt shl be pe dty1 dty0 (1) d7 (inc) address increment direction 1: x direction address increment 0: y direction address increment this bit sets the address increment direction of the di splay ram. the display ram address is automatically incremented by 1 every time data is written to the display da ta register. writing a ?1? to this bit sets ?x address increment,? and writing a ?0? sets ?y address increment. ? for further details regarding address incrementing, refer to the page entitled ?x, y address counter auto increment.? this bit is set to ?1? if the reset pin is pulled to a ?l? level.
fedl9092-01 oki semiconductor ml9092-01/02/03/04 47/66 (2) d6 (wls) (word length select) 1: 6-bit word length select 0: 8-bit word length select this bit selects the word length of data to be written to an d read from the display ram. if ?1? is written to this bit, data will be read from and written to the display ram in 6- bit units. if ?0? is written to this bit, data will be read from and written to the display ram in 8-bit units. this bit is reset to ?0? if the reset pin is pulled to a ?l? level. (3) d5 (kt) (key scan time) key scan time select bit 1: 10 ms 0: 5 ms this bit selects the key scan cycle time. in the case of a 306 khz oscillating frequency, writing a ?1? to this bit sets the key scan cycle time at 10 ms (1/3072 divided frequency of the oscillating frequency), writing a ?0? sets the key scan cycle time at 5 ms (1/1536 divided frequency of th e oscillating frequency). this bit is set to ?1? if the reset pin is pulled to a ?l? level. (4) d4 (shl) (common driver shift direction select bit) this bit selects the shift direction of common drivers. the relationship between this bit and shift directions are shown below. this bit is reset to ?0? if the reset pin is pulled to a ?l? level. shl duty shift direction 1/8 com8 com1 1/9 com9 com1 1 1/10 com10 com1 1/8 com1 com8 1/9 com1 com9 0 1/10 com1 com10 (5) d3 (be) (voltage doubler operation control bit ) this bit controls the operation of the voltage doubler. (applies to ml9092-01/02.) 1: voltage doubler enable 0: voltage doubler disable this bit is reset to ?0? if the reset pin is pulled to a ?l? level. (6) d2 (pe) (general-purpose port out put enable/disable select bit) this bit selects high impedance output or output enable for the general-purpose port outputs a, b, c and d (c and d apply to ml9092-01 only; b applies to ml9092-01/04). 1: output enable 0: high-impedance output (output disable) this bit is reset to ?0? if the reset pin is pulled to a ?l? level.
fedl9092-01 oki semiconductor ml9092-01/02/03/04 48/66 (7) d1, d0 (dty1, dty0) (display duty select bits) these bits select the display duty. the correspondence between each bit and display duty is shown in the chart below. these bits ar e reset to ?0? if the reset pin is pulled to a ?l? level. dty1 dty0 display duty 0 0 1/8 0 1 1/9 1 0 1/10 1 1 1/10 ? control register 2 (fcr2) d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 stb disp (1) d1 (stb) (standby mode select bit) this bit is used to control the standby and normal modes. (applies to ml9092-03/04.) 1: standby mode 0: normal mode this bit is reset to ?0? if the reset pin is pulled to a ?l? level. the lsi internal status and pin status during standby mode are as follows: - ram data is retained. - common output and segment output are v ss level. - electronic volume values are retained. - port output a is at a ?l? level (applies to ml9092-03/ 04). the status before standby is maintained for port output b (applies to ml9092-04). - rc oscillation is stopped. (oscillation is started with ke y input, maintained while the kreq output is at a ?h? level, and stopped when all key switches are turned off and the kreq output is at a ?l? level.) - rotary encoder input signals (a and b) are ignored. - key input allowed. - the microcontroller interface (cs, cp , di/o, kreq) is operable. (however, only with a kreq signal from the key scan, will the kreq pin output a ?h? level.) - v hin and v o should be set to v ss or the floating status. note: when there is a key input in a standby state, this ic will start oscillating and kreq output will go to a ?h? level. execute key scan reading periodically during this ?h? level period. also, execute key scan reading when the kreq signal changes from a ?h? to ?l? level. (2) d0 (disp) (display on/off mode bit) 1: display on mode 0: display off mode this bit selects whether the display is on or off. writin g a ?1? to this bit selects the display on mode. writing a ?0? to this bit selects the display off mode. at this time, the com and seg pins will be at the v ss level. even if this bit is set to ?0?, the displa y ram contents will not change. if the reset pin is pulled to a ?l? level, this register is reset to ?0?.
fedl9092-01 oki semiconductor ml9092-01/02/03/04 49/66 ? rotary encoder (re) read d7 d6 d5 d4 d3 d2 d1 d0 q4 q4 q4 q4 q4 q3 q2 q1 the rotary encoder read instruction is used to read the count value from the rotary encoder switch input signal. (count values are in the 2?s complement format.) (1) d7 to d0 (q4 to q1) (count value bit) the phase difference between the a signal and the b signal is recogn ized, and the value that is counted by the edge of the signal with the slower phase is set. count valu es range from negative 1000 (q4, q3, q2, q1) to positive 0111. if the count is less than negative 1000 or more than positive 0111, then it is ignored. these bits are all reset to ?0? when this instructi on is executed or when the reset pin is pulled to a ?l? level. if counterclockwise rotation is input after the count value is incremented by clockwise rotation, then count value will be decremented. if counterclockwise rotation is furt her input after the count value reaches 0000, then the count value will change to 1111 and the count value will be decremented. (the count value will remain 1000 even if counterclockwise rotation is further input after the count value reaches negative 1000.) after this, if clockwise rotation is input, then the count value will be incremented. if the count value reaches 1111 and clockwise rotation is further input, then the co unt value will become 0000 and the count value will be incremented. (even if clockwise rotation is further in put after the count value reach es positive 0111, the count value will maintain 0111.)
fedl9092-01 oki semiconductor ml9092-01/02/03/04 50/66 functional description of the rotary encoder switch as shown in figure 3, the rotary encoder switch circuit is made up of phase detection circuit, an interrupt generation circuit, an up/down counter and a parallel-in/serial-out register. phase detection circuit up down b a up/down counter parallel in/serial out shift register interrupt generation circuit to kreq output data q4 q3 q2 q1 figure 3 rotary encoder switch circuit 1) phase detection and interrupt generation circuits 1-1) clockwise rotation when the a and b signals are input as shown in figure 4, the phase detection circuit outputs the up signal after the chattering absorption period. at this time, the kreq output goes to a high level, so that this signal can be used as the interrupt signa l. the kreq signal maintains a high level until the rotary encoder read instruction is executed. up (internal signal) b a kreq chattering absorption period figure 4 input/output timing for clockwise rotation
fedl9092-01 oki semiconductor ml9092-01/02/03/04 51/66 1-2) counterclockwise rotation when the a and b signals are input as shown in fi gure 4, the phase detection circuit outputs the down signal after the chattering absorption period. at this time, the kreq output goes to a high level, so that this signal can be used as the interrupt signal. the kreq signal maintains a high level until the rotary encoder read instruction is executed. figure 5 input/output timing for counterclockwise rotation 2) up/down counter the up/down counter is incremented when an up signal is input and decremented when a down signal is input. however, if th e counter reaches ?0111? and an up signal is input, the up/down counter will hold ?0111?. in the same manner, if the up/down counter is at ?1000? and a down signal is input, the up/dow n counter will hold ?1000?. figure 6 when the up counter overflows figure 7 when the down counter overflows b a kreq chattering absorption period down (internal signal) b q 4, q3, q2, q1 a 0001 0010 0011 0100 0101 0110 0111 0111 b q4, q3, q2, q1 a 1111 1110 1101 1100 1011 1010 1001 1000 1000
fedl9092-01 oki semiconductor ml9092-01/02/03/04 52/66 3) parallel-in/serial-out shift register the kreq signal goes to a low le vel when the rotary encoder read instruction is ex ecuted, when the up/down counter will be reset to ?0?. figure 8 operation of kreq output notes: 1. the kreq signal is output by a logical or of the kreq signal generated by a key scan and the kreq signal generated by the rotary encoder. the kr eq signal from the rotary encoder is reset by executing the rotary encoder read instruction; however, the kreq signal generated by a key scan is not reset even if the key scan regi ster read instruction is executed. also, if the kreq signal is generated by a key scan, it will not be reset even if the rotary encoder read instruction is executed. although dependent on the components glued to this lsi, it is recommended that the rotary encoder read instruction and key scan register read instru ction be executed as a set when the kreq signal goes to a ?h? level. 2. the maximum read cycle time for when the kreq si gnal is at a ?h? level is practically determined by the signal input from the rotary encoder and the 3-bit co unter built into this lsi. therefore, make the time taken before starting to execute the ro tary encoder read instruction 12 ms or less. 3. using a rotary encoder switch that has the click stabilizing points shown below is recommended. click stabilizing points a signal b signal waveform of a recommended rotary encoder switch c s cp di/o 1 2 8 9 11 10 12 13 14 15 16 instruction code read data1 output state input state kreq
fedl9092-01 oki semiconductor ml9092-01/02/03/04 53/66 ? contrast adj (ca) set d7 d6 d5 d4 d3 d2 d1 d0 ? ? ? ? ct3 ct2 ct1 ct0 ?: don?t care this instruction is for adjusting the liquid crystal display voltage. (1) d3 to d0 (ct3 to ct0) (contrast adjustment value setting bits) when fh is written to these bits, the liquid crystal display voltage (voltage between the v 0 and v ss pins) becomes a maximum. when 0h is written, the liquid crystal display voltage becomes a minimum. by setting the values from 0h to fh, the liquid crystal display voltage can be adjusted just like an electronic volume control. these bits are all re set to ?0? if the reset pin is pulled to a ?l? level. v 0 ouput target voltage for contrast adj setting values contrast adj setting values v 0 output target voltage ct3 ct2 ct1 ct0 ml9092-01/02 ml9092-03/04 1 1 1 1 0.980v out 0.980v hin 1 1 1 0 0.973v out 0.973v hin 1 1 0 1 0.947v out 0.947v hin 1 1 0 0 0.923v out 0.923v hin 1 0 1 1 0.900v out 0.900v hin 1 0 1 0 0.878v out 0.878v hin 1 0 0 1 0.857v out 0.857v hin 1 0 0 0 0.837v out 0.837v hin 0 1 1 1 0.818v out 0.818v hin 0 1 1 0 0.800v out 0.800v hin 0 1 0 1 0.783v out 0.783v hin 0 1 0 0 0.766v out 0.766v hin 0 0 1 1 0.750v out 0.750v hin 0 0 1 0 0.735v out 0.735v hin 0 0 0 1 0.720v out 0.720v hin 0 0 0 0 0.700v out 0.700v hin
fedl9092-01 oki semiconductor ml9092-01/02/03/04 54/66 ? pwm0/1/2 register (pwmr) set d7 d6 d5 d4 d3 d2 d1 d0 pwx7 pwx6 pwx5 pwx4 pwx3 pwx2 pwx1 pwx0 note: ?x? stands for 0 for pb0 (port b0), 1 for pb1 (port b1) and 2 for pb2 (port b2). this instruction sets the pulse width of the pwm signal output from port b. (applies to ml9092-01/04.) pwx0 is lsb and pwx7 is msb. this instruction should be used with a pwm data write cycle of 5.0 ms or longer. these bits are all re set to ?0? if the reset pin is pulled to a ?l? level. note: when inputting multiple pwm data items, be sure to input them in succession (i.e., without intervals). pwxn = 00 h (0/255) fixed at ?h? state at the time of reset pwxn = 01 h (1/255) pwxn = 02 h (2/255) pwxn = 03 h (3/255) pwxn = fe h (254/255) pwxn = ff h (255/255) fixed at ?h? ? test register (test) set d7 d6 d5 d4 d3 d2 d1 d0 ? ? ? ? t4 t3 t2 t1 ?: don?t care this instruction is for testing by the manufacturer. customers should not use this register. figure 9 pwm output waveform
fedl9092-01 oki semiconductor ml9092-01/02/03/04 55/66 display screen and memory address allocation the ml9092-01/02/03/04 has an internal display data ram (60 bits by 10 bits) of a bitmap type. the allocation of memory addresses varies according to the selected word length (6 bits or 8 bits) as shown in figure 10: 0 to 7 for selection of 8 bits per word or 0 to 9 for selection of 6 bits per word. the x address 7 in the 6-bits/word mode has four display memory bits. the four bits (d7 to d4) starting from bit d7 of the display data register are written in me mory and the other bits (d3 to d0) are ignored. address allocation in the 8-bits/word mode address allocation in the 6-bits/word mode 0 1 2 7 0 1 9 (x address) (y address) (d7) (d0) (8 bits) (d7) (d4) (4 bits) 0 1 2 9 0 1 9 (x address) (d5) (d0) (6 bits) (y address) figure 10 display memory addresses in the 8-bits/word mode, data to be displayed is written in display memory with the d7 data of the display data register at address (xn, yn) and the d0 data at address (xn + 7, yn). similarly, in the 6-bits/word mode, data to be displayed is written in display memory with the d5 data of the display data register at address (xn, yn) and the d0 data at address (xn + 5, yn). see figure 11. data ?1? in display memory represents turning on the corresponding display segment and data ?0? in display memory represents turning off the corresponding display segment. note: in the ml9092-01, the x address range in the 8-bits/mode will be 0 to 6 segment output 0 0 0 0 (seg1) (seg2) (seg3) (seg4) (seg5) (seg6) (seg7) (seg8) 11 1 1 1 y line y0 y1 y9 common output (com1) (com2) (com10) ram for 60 dots by 10 dots display (d7) (d5) (d0) for 8 bits per word (seg60) x0 x1 x2 x3 x4 x5 x6 x7 x59 x line (d0) for 6 bits per word figure 11 display screen bit allocation and memory addresses
fedl9092-01 oki semiconductor ml9092-01/02/03/04 56/66 x ? y address counter auto increment the liquid crystal display ram has an x-address counter and a y-address counter. each address counter has an auto increment function. when display data is read or written, this function increments either of thes e x- and y-address c ounters (which is selected by the inc bit (d7 bit) of the control register 1). inc bit = ?0? selects the y-address counter. inc bit = ?1? selects the x-address counter. the address counting cycle of the x addres s counter varies according to the selected word length (8 bits or 6 bits): x address range of 0 to 6 (ml9092-01) or 0 to7 (ML9092-02/03/04) in the 8-bits/word mode or x address range of 0 to 9 in the 6-bits/word mode. when the x address count returns to 0 from a maximum value (6 (ml9092-01) or 7 (ML9092-02/03/04) in the 8-bits/word mode, or 9 in the 6-bits/word mode), the y address is also incremented automatically. the relationship between display duties and y address count ranges is shown below. when the y-address counter returns to 0 from a maximum value, the x address is also incremented automatically. model duty y-address count range (cycle) maximum y address count 1/8 0 to 7 7 1/9 0 to 8 8 ml9092-01/02/03/04 1/10 0 to 9 9 note: if an invalid address (outside the address count ra nge) is given to the x- or y- address counter, its counting will not be assured. example of incrementing the x-address example of incrementing the y-address (8 bits per word and 1/10 duty) (8 bits per word and 1/10 duty) 0 1 2 7 0 x address 1 9 y address 0 0 x address y address 1 7 1 2 9
fedl9092-01 oki semiconductor ml9092-01/02/03/04 57/66 liquid crystal driving waveform example (1) 1/8 duty (1/4 bias) 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 v 0 v 1 v 2 c0m1 v 3 v ss v 0 v 1 v 2 c0m2 v 3 v ss v 0 v 1 v 2 c0m8 v 3 v ss common line no. a non-selectable waveform is output from com9 and com10 outputs. 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 v 0 v 1 v 2 segn v 3 v ss : light on : light off common line no.
fedl9092-01 oki semiconductor ml9092-01/02/03/04 58/66 liquid crystal driving waveform example (2) 1/9 duty (1/4 bias) 9 1 2 3 4 5 6 7 89 1 2 3 4 5 6 7 8 9 1 v 0 v 1 v 2 c0m1 v 3 v ss v 0 v 1 v 2 c0m2 v 3 v ss v 0 v 1 v 2 c0m9 v 3 v ss common line no. a non-selectable waveform is output from the com10 output. 9 1 2 3 4 5 6 7 89 1 2 3 4 5 6 7 8 9 1 v 0 v 1 v 2 segn v 3 v ss : light on : light off common line no.
fedl9092-01 oki semiconductor ml9092-01/02/03/04 59/66 liquid crystal driving waveform example (3) 1/10 duty (1/4 bias) 10 1 2 3 4 5 6 7 89 1 2 3 4 5 6 7 8 9 v 0 v 1 v 2 c0m1 v 3 v ss 10 10 v 0 v 1 v 2 c0m2 v 3 v ss v 0 v 1 v 2 c0m10 v 3 v ss common line no. 10 1 2 3 4 5 6 7 89 1 2 3 4 5 6 7 8 9 v 0 v 1 v 2 segn v 3 v ss 10 10 : light on : light off common line no.
fedl9092-01 oki semiconductor ml9092-01/02/03/04 60/66 flowchart for setting the standby mode and releas ing the standby setting with kreq by key input (applies to the ml9092-03/04) normal operaton set disp of control register 2 to ?1? displaying of initial screen started settings completed no yes make a setting for registers again is initial screen data input complete? make a setting of inc, wls, kt, shl, be, pe, dty1, and dty0 again make a setting for port register a and display data ram again according to the specification. standby state standby state make a setting for control registe r 2 again lcd driving voltage: on ke y in p ut make a setting for control register 2 no yes kreq output = ?h? level ? release stb. setting of stb and disp lcd driving voltage: off pull v hin and v 0 to the v ss level or put them into a floating state. turn external power supply (v hin ) off make a setting for control register 2 turn external power supply (v hin ) on
fedl9092-01 oki semiconductor ml9092-01/02/03/04 61/66 power-on flowchart start make a setting for control register 1 displaying of initial screen started setting complete no yes is input of initial screen data complete ? external reset or power-on reset make a setting for inc, wls, kt, shl, be, pe, dty1, and dty0. make a setting for port register a, port register b, port register c, port register d, and display data ram according to specifications. turn on v dd turn on v in input reset signal make a setting for registers wait till the liquid crystal driving voltage stabilization time is reached set disp of control register 2 to ?1? wait till the vout voltage stabilizes when the voltage doubler is used. power-off flowchart lcd driving state turn off v in turn off v dd [caution] ? the lines between output pins, and between output pins and other pins (input pins, i/o pins or power supply pins), should not be short circuited.
fedl9092-01 oki semiconductor ml9092-01/02/03/04 62/66 precautions when turning on the power supply to prevent the device from malfunctioning, observe the following power-on/off sequence: for power-on, first turn on the logic power supply (v dd ), then turn on the voltage doubler reference voltage (v in ) or high voltage (v out or v hin ). for power-off, first turn off the voltage doubler reference voltage (v in ) or high voltage (v out or v hin ), then turn off the logic power supply (v dd ). [voltage] [time] v dd pin voltage v dd = 2.0 v power-on sequence v out or v hin pin voltage
fedl9092-01 oki semiconductor ml9092-01/02/03/04 63/66 application circuit application example?1/10 duty, 1/4 bias, voltage doubler used (internal contrast adjustment not used) ml9092-01 v in v cc v c1 + v s1 ? + 4.7 f v out v 0 + 4.7 f pwm output ports 5 5 key matrix c0/d0 c1/d1 c2/d2 c3/d3 c4/d4 v dd kps v ss pa0 osc1 osc2 56 k ? tes t r ese t v dd = 5 v r0/c0 r1/c1 r2/c2 r3/c3 r4/c4 seg1?56 com1?com10 lcd panel temperature compensat- ing and stabilizing circuits 56 f pb0?pb2 cp di/o c s kreq port or serial port cpu a , b rotary switch l.p.f.
fedl9092-01 oki semiconductor ml9092-01/02/03/04 64/66 package dimensions tqfp100-p-1414-0.50-k mirror finish package material epoxy resin lead frame material 42 alloy pin treatment solder plating ( 5m) package weight (g) 0.55 typ. 5 rev. no./last revised 4/oct. 28, 1996 notes for mounting the surface mount type package the surface mount type packages ar e very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform refl ow mounting, contact oki?s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). (unit: mm)
fedl9092-01 oki semiconductor ml9092-01/02/03/04 65/66 revision history page document no. date previous edition current edition description fedl9092-01 nov. 4, 2003 ? ? first edition
fedl9092-01 oki semiconductor ml9092-01/02/03/04 66/66 notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. when planning to use the product, please ensure that the external conditions are reflected in the actual circu it, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improp er installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third part y?s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third party?s right which may result from the use thereof. 6. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communicati on equipment, measurement equipment, consumer electronics, etc.). these products are not, unless specifica lly authorized by oki, authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications includ e, but are not limited to, traffic and auto motive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. no part of the contents contained herein may be reprinted or reproduced without our prior permission. copyright 2003 oki electric industry co., ltd.

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